BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//IEEE Region 6 - ECPv6.16.5//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:IEEE Region 6
X-ORIGINAL-URL:https://www.ieeer6.org
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REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20270314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20271107T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260806T160000
DTEND;TZID=America/Los_Angeles:20260806T170000
DTSTAMP:20260629T164213Z
CREATED:20260628T164251Z
LAST-MODIFIED:20260629T164213Z
UID:10000635-1786032000-1786035600@www.ieeer6.org
SUMMARY:Dual Seed Semi-Additive and Damascene Processes: Enabling Fine-Pitch Interconnects for Advanced Packaging
DESCRIPTION:[]\nAs AI\, high-performance computing\, and heterogeneous integration continue to scale\, advanced packaging is facing growing interconnect challenges across redistribution layers\, IC substrates\, HDI boards\, silicon vias\, and emerging glass-core platforms. Higher bandwidth and larger package form factors require finer wiring\, smaller vias\, higher fan-out density\, and more reliable vertical interconnects. In this context\, copper seed formation and via metallization are becoming increasingly important bottlenecks for next-generation package and substrate scaling.\nConventional copper deposition technologies\, including physical vapor deposition\, electroless plating\, and electroplating\, each play essential roles in today’s manufacturing flows. However\, as via structures become smaller\, deeper\, rougher\, or higher in aspect ratio\, limitations such as step coverage\, liquid circulation\, process uniformity\, and seed-layer continuity become more difficult to manage. These challenges are especially relevant across multiple interconnect layers\, including motherboard HDI PCBs\, IC substrates\, RDL\, memory and interposer silicon vias\, and Si BEOL metal\, etc.\nThis presentation will introduce Nano Copper Deposition as a solution family for AI-era interconnect scaling. The talk will cover DeepVia™ HDI for high-aspect-ratio via metallization in motherboard HDI PCBs\, DS-SAP™ for resolving the trade-off between thin surface seed layers and robust via coverage in IC substrates\, and other applications such as Dual Seed Damascene for fine and high-aspect-ratio damascene structures in BEOL and RDL applications\, and DeepVia™ Silicon for memory and interposer silicon vias. The discussion will highlight how these approaches can support higher I/O density\, improved escape routing\, reduced layer-count dependency\, and broader process flexibility for next-generation advanced packaging.\nSpeaker(s): Shinya Shimizu\,\nVirtual: https://events.vtools.ieee.org/m/565310
URL:https://www.ieeer6.org/event/dual-seed-semi-additive-and-damascene-processes-enabling-fine-pitch-interconnects-for-advanced-packaging/
LOCATION:Virtual: https://events.vtools.ieee.org/m/565310
CATEGORIES:Local Events
ATTACH;FMTTYPE=image/jpeg:https://www.ieeer6.org/wp-content/uploads/ieee-region-6-event-01.jpg
END:VEVENT
END:VCALENDAR