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DTSTART;TZID=America/Los_Angeles:20260924T113000
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UID:10000659-1790249400-1790254800@www.ieeer6.org
SUMMARY:Glass-Core Packaging and Its Reliability
DESCRIPTION:In the past few years\, because of high-performance computing (HPC) driven by artificial intelligence (AI) and data centers in this AI era\, packaging using glass-core substrates has been attracting lots of traction. For example\, among others\, Intel’s one-trillion-transistors application processor with glass-core substrate is to be shipped by the end of 2030 (announced September 2023) and TSMC’s chip-on-panel-on-substrate (CoPoS) with glass-core interposer is to be shipped in Q1 of 2029 (announced April 2025). In this lecture\, a brief fundamental of through-glass via (TGV) and redistribution-layers (RDLs) of glass packaging will be presented. The advantages and disadvantages of glass\, silicon\, and organic will be discussed. Panel-level packaging vs. wafer-level packaging and the panel size will also be provided. Finally\, the effects of coefficient of thermal expansion (CTE) of glass-core substrate on the solder joint reliability on printed circuit board (PCB) will be presented. Some recommendations will be provided.\nSpeaker(s): John Lau\,\nSEMI World Headquarters\, 673 South Milpitas Blvd\, Milpitas\, California\, United States\, 95050
URL:https://www.ieeer6.org/event/glass-core-packaging-and-its-reliability/
LOCATION:SEMI World Headquarters\, 673 South Milpitas Blvd\, Milpitas\, California\, United States\, 95050
CATEGORIES:Local Events
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