BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//IEEE Region 6 - ECPv6.17.1//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:IEEE Region 6
X-ORIGINAL-URL:https://www.ieeer6.org
X-WR-CALDESC:Events for IEEE Region 6
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Guatemala
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:20250101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Guatemala:20260717T121000
DTEND;TZID=America/Guatemala:20260717T163000
DTSTAMP:20260717T181216Z
CREATED:20260707T171304Z
LAST-MODIFIED:20260717T181216Z
UID:10000651-1784290200-1784305800@www.ieeer6.org
SUMMARY:IEEE Albuquerque SSCS/EDS Joint Chapter: Inaugural Talk
DESCRIPTION:PART I: The Road to Gate-All-Around CMOS (07/17 — 12:10PM )\nDespite the much debated end of Moore's Law\, CMOS scaling still maintains economic relevance with 2nm gate-all-around SoCs anticipated in the coming quarters. Area scaling extensively driven by design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power\, performance\, area\, and cost benefits. In this tutorial\, we will start with a walk through memory lane\, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes\, highlighting the resulting technology characteristics and challenges. This will set the stage for transitioning to the nanoribbon gate-all-around (GAA) transistor architecture and unveiling the magic of how these devices are fabricated.\nPart II: The Road to Gate-All-Around and Its Impact on Analog Design (07/17 — 2:30PM )\nEmbrace the technology – the essence of how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling. This presentation will cover the impact of advanced CMOS on analog design\, and examples of the creativity of analog designers to preserve and extend the performance of traditional analog functions. We will finally take a look at technologies on the horizon and suggest how they will impact the future of analog design based on the challenges that CMOS scaling has imposed. To address the growing effort required for analog/mixed-signal design\, we will cover design strategies on how analog design has adapted and thrived through decades of increasingly unfriendly scaling\, including the migration to heterogeneous integration.\nSpeaker(s): \, Alvin\nAgenda:\nPART I (07/17 — 12:10PM):\nThe Road to Gate-All-Around CMOS ( 12:10-1:30PM )\nQ&A ( 1:30-2:00PM )\nBreak\, complimentary snacks/drinks.( 2:00-2:30PM )\nPART II (07/17 — 2:30PM):\nThe Road to Gate-All-Around CMOS ( 2:30-4.00PM )\nQ&A ( 4.00-4.30PM )\nBreak\, complimentary snacks/drinks.( 4.30-5:00PM )\nRoom: 1NEO\, Bldg: RR5\, 1600 Rio Rancho Blvd SE\, Rio Rancho\, New Mexico\, United States\, 87124\, Virtual: https://events.vtools.ieee.org/m/566775
URL:https://www.ieeer6.org/event/ieee-albuquerque-sscs-eds-joint-chapter-inaugural-talk/
LOCATION:Room: 1NEO\, Bldg: RR5\, 1600 Rio Rancho Blvd SE\, Rio Rancho\, New Mexico\, United States\, 87124\, Virtual: https://events.vtools.ieee.org/m/566775
CATEGORIES:Local Events
ATTACH;FMTTYPE=image/jpeg:https://www.ieeer6.org/wp-content/uploads/ieee-region-6-event-01.jpg
END:VEVENT
END:VCALENDAR