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SUMMARY:The Making of a Chip: Technology\, Tools\, and Careers
DESCRIPTION:The Making of a Chip is an introductory technical and career-focused session designed to provide participants with a comprehensive overview of the complete ASIC development lifecycle. The event will guide attendees through each critical phase of chip creation\, starting from system and ASIC/VLSI specifications\, progressing through design and verification\, and concluding with post-silicon validation.\nParticipants will gain insights into how real-world requirements are translated into silicon-ready designs\, the role of RTL design and functional verification\, and the importance of validation after fabrication to ensure performance\, reliability\, and compliance. In addition to the technical flow\, the session will highlight current industry practices\, tools\, and skills required at each stage of the semiconductor lifecycle.\nThe event will also focus on career opportunities for graduates in the semiconductor industry\, outlining various job roles such as ASIC/VLSI design engineer\, verification engineer\, validation engineer\, and related entry-level positions. Industry expectations\, essential skill sets\, and career pathways will be discussed to help students and early-career professionals prepare for roles in chip design and development.\nThis session is ideal for engineering students and graduates who are interested in understanding ASIC/VLSI design workflows and exploring career opportunities in the semiconductor domain.\nAgenda:\nAgenda\n6:00 PM – 6:15 PM\nWelcome Note & Event Overview\n6:15 PM – 7:15 PM\nThe Making of a Chip: Technology\, Tools\, and Careers – Big picture\nSpeakers – Jigneshkumar Patel (AMD)\, Venupradeepa Kolari (Intel) and Amiraj Nigam (Intel)\, Lalatendu Satpathy (Intel)\n7:15 PM – 8:00 PM\nResume Review & 1-to-1 Mentoring with Graduates\nJigneshkumar Patel (AMD)\, Venupradeepa Kolari (Intel)\, Amiraj Nigam (Intel)\, Lalatendu Satpathy (Intel)\, Arvind Akula (Rate Inc)\, Anurag (Intel)\n🍕 Pizza will be served.\nIf you’re looking for a mentor or hoping to expand your professional network\, this is the perfect chance to connect and learn from experts and peers.\nRoom: 1015\, Bldg: Riverside Hall\, 6000 J Street\, Sacramento\, California\, United States\, 95819
URL:https://www.ieeer6.org/event/specification-to-silicon-a-complete-overview-of-the-semiconductor-lifecycle-and-careers/
LOCATION:Room: 1015\, Bldg: Riverside Hall\, 6000 J Street\, Sacramento\, California\, United States\, 95819
CATEGORIES:Local Events
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