[]This no-cost workshop brings together five industry experts (plus an optional lab tour) to discuss the latest 2.5D/3D/3.5D semiconductor packaging solutions for HPC and AI. It highlights the growing challenges of fault isolation (FI) and failure analysis (FA) in dense interconnects such as hybrid bonding and micro bump arrays, reviews new thermal management options (metallic TIMs, low-temp solders), showcases advanced non-destructive inspection tools (computed laminography and high resolution CT), and introduces cutting edge microscopy techniques (SAM and PiFM) for defect characterization, while outlining emerging FI-FA workflows and tool roadmaps for reliable, scalable AI and data center hardware. Attendees will gain insight into current industry troubleshooting workflows and a forward-looking roadmap of the tools and techniques being developed to address advanced packaging failures. Additionally, the optional lab tour can help the attendees understand the tools and techniques discussed in the lectures.
Four guided training talks with small-group interaction:
9:00: Advanced Packaging for AI – Challenges and Roadmaps in Fault Isolation and Failure Analysis
9:30: Metal TIM and Low-Temp Solder Paste for HPC and AI Industry Challenges
10:00: Failure Analysis of Electronic Components for AI and Data Center Infrastructure
10:30: High-Resolution 3D X-Ray Inspection for Advanced Packaging Integration
11:00: Scanning Acoustic Microscopy (SAM) and Photo-induced Force Microscopy (PiFM) for Defect Identification and Characterization in AI Hardware
11:30: lunch, social/networking, and optional lab tours
Speaker(s): Yan Li, David Hu, Audrey Chamoire , Jeff Gelb, Austin Barnes
Covalent Corp., 925 Thompson Place, Sunnyvale, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/575155
